Functional safety failure rates of Logic elements

The component failure rate (FIT) for Logic elements depends on the technology used in the logic element.

Reliability data originating in Siemens Norm SN 29500-2:

Important: The SN29500-2 FIT data depends on the semiconductor technology:

• TTL, TTL-LS, TTL-ALS & TTL-F:
  • with ≤ 10 inputs + outputs (= SSI/MSI): 2 FITs (with a reference virtual $T_J$ of 45°C)
  • with > 10 inputs + outputs (= LSI): 4 FITs (with a reference virtual $T_J$ of 55°C)
• TTL-S:
  • with ≤ 10 inputs + outputs (= SSI/MSI): 4 FITs (with a reference virtual $T_J$ of 45°C)
  • with > 10 inputs + outputs (= LSI): Not specified in SN 29500-2
• ECL: Depends on the number of ECL gates and the family see table 3 in SN 29500-2
  • 10k: 10 FITs for a reference virtual $T_J$ of 65°C
  • 100k: 15 FITs for a reference virtual $T_J$ of 75°C
  • LVECL/PECL/Low power ECL/ECLinPS: 15 FITs for a reference virtual $T_J$ of 60°C
• HCMOS/CMOS B/ACMOS (FCT, HC, AC, AUC, LVX, LVC, LCX, LV, VCX, ALVC, AVC, AHC & VHC):
  • with ≤ 10 inputs + outputs (= SSI/MSI): 3 FITs (with a reference virtual $T_J$ of 45°C and a reference supply voltage of 5V)
  • with > 10 inputs + outputs (= LSI): 5 FITs (with a reference virtual $T_J$ of 45°C and a reference supply voltage of 5V)
• BiCMOS logic gates:
  • with ≤ 10 inputs + outputs (= SSI/MSI): 3 FITs (with a reference virtual $T_J$ of 45°C)
  • with > 10 inputs + outputs (= LSI): 5 FITs (with a reference virtual $T_J$ of 55°C)

The FITs for naked (= unpackaged) chips must be multiplied by a factor of 2.